In recent years, with progress in miniaturization and performance upgrades of electronic information equipment, great efforts have been made to develop technology for increasing the density of semiconductor packages and of other semiconductor devices mounted on them. The BGA (Ball Grid Array) structure is a structure for increasing the density of semiconductor packages. FIG. 10 is a diagram illustrating an example of the basic constitution of a semiconductor package adopting a BGA structure. In this semiconductor package, semiconductor chip 900 having an integrated circuit formed on its principal surface (upper surface shown in the figure) is attached via die bonding paste 904 to insulating substrate (substrate) 902, and is sealed with sealant 918. Electrode pads 920 led out from the integrated circuit are formed on the surface of semiconductor chip 900. A conductor pattern is formed on the principal surface of insulating substrate 902 for connecting electrode pads 920 of semiconductor chip 900 to solder bumps 908 serving as external connecting terminals. This conductor pattern includes lands 930 that are connected to electrode pads 920 of semiconductor chip 900 via conductor wires 910, and connecting pads 932 connected to solder bumps 908 via through holes formed in insulating substrate 902.
FIG. 11 is a plan view illustrating the conductor pattern on insulating substrate 902. Lands 930 of the conductor pattern are arranged along the outer periphery of semiconductor chip 100 assembled on insulating substrate 902. Connecting pads 932 are arranged 2-dimensionally in the inner region of insulating substrate 902. Lands 930 and connecting pads 932 are connected to each other by means of leads 934. As shown in FIG. 12, an enlarged plan view, each land 930 has a rectangular planar shape with a constant width W (about 0.1 mm). Conductor wire 910 is bonded to its surface.
In recent years, in order to meet the requirements for higher density of semiconductor packages, there has been demand for an increase in the number of pins without a change in the package size. For this purpose, it is necessary to reduce the arrangement pitch of lands 930 in order to increase the arrangement density. However, when the arrangement pitch of lands 930 is reduced, the following problems arise.
That is, because each land 930 has an area (wire connection enablement area R) that allows conductor wire 910 to be connected during bonding, it is necessary to ensure that said wire connection enablement areas R do not overlap each other in order to prevent mutual contact between conductor wires 910. It is known that said wire connection enablement areas R have a fan shape with radius of 0.25 mm and fan angle of 30° C. Consequently, in order to preserve such areas, it is necessary to have an arrangement pitch for lands 930 of about 0.13 mm or larger.
On the other hand, in order to preserve wire connection enablement areas R, a zigzag configuration has been proposed, as shown in FIG. 13, in which lands 930 are arranged offset from each other alternately toward the outer side and toward the inner side of insulating substrate 902 (FIG. 11). However, in this case, gap C between lands 930 becomes too narrow, and manufacturing becomes difficult using the present available etching process capability (which requires a gap of 30 μm or larger). This is undesirable.
The purpose of this invention is to solve the aforementioned problems of the conventional methods by providing a type of substrate for carrying a semiconductor chip that can increase the arrangement density of lands, and a type of semiconductor device using said substrate for carrying a semiconductor chip.